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128k x 36 synchronous-pipelined cache sram cy7c1347d cypress semiconductor corporation ? 3901 north first street ? san jose , ca 95134 ? 408-943-2600 document #: 38-05022 rev. *e revised november 11, 2004 features ? fast access times: 2.5 and 3.5 ns ? fast clock speed: 250, 225, 200, and 166 mhz ? 1.5-ns set-up time an d 0.5-ns hold time ? fast oe access times: 2.5 ns and 3.5 ns ? optimal for depth expansion (one cycle chip deselect to eliminate bus contention) ? 3.3v ?5% and +10% power supply ? 3.3v or 2.5v i/o supply ? 5v tolerant inputs except i/os ? clamp diodes to v ss at all inputs and outputs ? common data inputs and data outputs ? byte write enable and global write control ? three chip enables for depth expansion and address pipeline ? address, data, and control registers ? internally self-ti med write cycle ? burst control pins (interleaved or linear burst sequence) ? automatic power-down for portable applications ? jtag boundary scan ? jedec standard pinout ? low profile 119-lead, 14 -mm x 22-mm bga (ball grid array) and 100-pin tqfp packages functional description this cypress synchronous burst sram employs high-speed, low-power cmos designs using advanced triple-layer polysilicon, double-layer metal technology. each memory cell consists of four transistors and two high-valued resistors. the cy7c1347d sram integrate 131,072 x 36 sram cells with advanced synchronous peripheral circuitry and a 2-bit counter for internal burst operation. all synchronous inputs are gated by registers controlled by a positive-edge-triggered clock input (clk). the synchronous inputs include all addresses, all data inputs, address-pipelining chip enable (ce ), depth-expansion chip enables (ce2 and ce2), burst control inputs (adsc , adsp , and adv ), write enables (bwa , bwb , bwc , bwd , and bwe ), and global write (gw ). asynchronous inputs include the output enable (oe ) and burst mode control (mode). the data outputs (q), enabled by oe , are also asynchronous. addresses and chip enables are registered with either address status processor (adsp ) or address status controller (adsc ) input pins. subsequent burst addresses can be internally generated as c ontrolled by the burst advance pin (adv ). address, data inputs, and write co ntrols are registered on-chip to initiate self-tim ed write cycle. write cycles can be one to four bytes wide as controlled by the write control inputs. individual byte write allows individual byte to be written. bwa controls dqa. bwb controls dqb. bwc controls dqc. bwd controls dqd. bwa , bwb , bwc , and bwd can be active only with bwe being low. gw being low causes all bytes to be written. four pins are used to implement jtag test capabilities: test mode select (tms), test data-i n (tdi), test clock (tck), and test data-out (tdo). the jtag circ uitry is used to serially shift data to and from the device. jtag inputs use lvttl/lvcmos levels to shift data during this testing mode of operation. the cy7c1347d operates from a +3.3v power supply. all inputs and outputs are lvttl-compatible selection guide cy7c1347d-250 cy7c1347d-225 cy7c1347d-200 cy7c1347d-166 maximum access time (ns) 2.5 2.5 2.5 3.5 maximum operating current (ma) 450 400 360 300 maximum cmos standby current (ma) 10 10 10 10 [+] feedback
cy7c1347d document #: 38-05022 rev. *e page 2 of 21 note: 1. the functional block diagram illustrates simplified device oper ation. see truth table, pin descriptions and timing diagrams f or detailed information. functional block diagram?cy7c1347d [1] dq dq bwc# bwe# bwd# ce# ce2 ce2# byte c write byte d write output register oe# byte c write adsp# adsc# address register binary counter & logic clr a a1-a0 adv# mode 128k x 9 x 4 sram array output buffers input register byte d write dqa,dqb dqc,dqd dq dq dq bwa# bwb# gw# byte a write byte b write clk byte b write byte a write dq dq enable power down logic zz 15 [+] feedback
cy7c1347d document #: 38-05022 rev. *e page 3 of 21 pin configurations 100-pin tqfp top view a a a a a1 a0 tms tdi v ss v cc tck a a a a a dqb dqb dqb v ccq v ss dqb dqb dqb dqb v ss v ccq dqb dqb v ss nc v cc dqa dqa v ccq v ss dqa dqa dqa dqa v ss v ccq dqa dqa dqa dqc dqc dqc v ccq v ss dqc dqc dqc dqc v ss v ccq nc v cc nc v ss v ccq v ss dqd v ss v ccq dqd dqd dqd a a ce ce2 bwd bwc bwb bwa ce2 v cc v ss clk gw bwe oe adsp a a 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 a adv adsc zz tdo mode a cy7c1347d dqc dqc dqd dqd dqd dqd dqd [+] feedback
cy7c1347d document #: 38-05022 rev. *e page 4 of 21 cy7c1347d pin descriptions bga pins qfp pins name type description 4p 4n 2a, 3a, 5a, 6a, 3b, 5b, 2c, 3c, 5c, 6c, 2r, 6r, 3t, 4t, 5t 37 36 35, 34, 33, 32, 100, 99, 82, 81, 44, 45, 46, 47, 48, 49, 50 a0 a1 a input- synchronous addresses: these inputs are registered and must meet the set-up and hold times around the rising edge of clk. the burst counter generates internal addresses associated with a0 and a1, during burst cycl e and wait cycle. 5l 5g 3g 3l 93 94 95 96 bwa bwb bwc bwd input- synchronous byte write: a byte write is low for a write cycle and high for a read cycle. bwa controls dqa. bwb controls dqb. bwc controls dqc. bwd controls dqd. data i/o are high impedance if either of these inputs are low, conditioned by bwe being low. 4m 87 bwe input- synchronous write enable: this active low in put gates byte write operations and must meet the set-up and hold times around the rising edge of clk. 4h 88 gw input- synchronous global write: this active low input allows a full 36-bit write to occur independent of the bwe and bwn lines and must meet the set-up and hold times around the rising edge of clk. 4k 89 clk input- synchronous clock: this signal registers the addresses, data, chip enables, write control and burst control inputs on its rising edge. all synchronous inputs must meet set-up and hold times around the clock?s rising edge. 4e 98 ce input- synchronous chip enable: this active low input is used to enable the device and to gate adsp . 6b 92 ce2 input- synchronous chip enable: this active low input is used to enable the device. 2u 38 tms input ieee 1149.1 test inputs. lvtt l-level inputs. if jtag feature is not utilized, this pin can be disconnected or connected to v cc. pin configurations (continued) 119-ball bga top view 1234567 a v ccq a a adsp aav ccq b nc ce2 a adsc ace2 nc c nc a a v cc aanc d dqc dqc v ss nc v ss dqb dqb e dqc dqc v ss ce v ss dqb dqb f v ccq dqc v ss oe v ss dqb v ccq g dqc dqc bwc adv bwb dqb dqb h dqc dqc v ss gw v ss dqb dqb j v ccq v cc nc v cc nc v cc v ccq k dqd dqd v ss clk v ss dqa dqa l dqd dqd bwd nc bwa dqa dqa m v ccq dqd v ss bwe v ss dqa v ccq n dqd dqd v ss a1 v ss dqa dqa p dqd dqd v ss a0 v ss dqa dqa r nc a mode v cc nc a nc t nc nc a a a nc zz u v ccq tms tdi tck tdo nc v ccq [+] feedback
cy7c1347d document #: 38-05022 rev. *e page 5 of 21 2u 39 tdi input ieee 1149.1 test inputs. lvtt l-level inputs. if jtag feature is not utilized, this pin can be disconnected or connected to v cc. 3u 43 tck input ieee 1149.1 test inputs. lvtt l-level inputs. if jtag feature is not utilized, this pin can be disconnected or connected to v ss or v cc. 5u 42 tdo output ieee 1149.1 test output. lvttl-level out put. if jtag feature is not utilized, this pin should be disconnected. 1b, 7b, 1c, 7c, 4d, 3j, 5j, 4l, 1r, 5r, 7r, 1t, 2t, 6t, 6u 14, 16, 66 nc ? no connect: these signals are not internally connected. cy7c1347d pin descriptions (continued) bga pins qfp pins name type description burst address table (mode = nc/v cc ) first address (external) second address (internal) third address (internal) fourth address (internal) a...a00 a...a01 a...a10 a...a11 a...a01 a...a00 a...a11 a...a10 a...a10 a...a11 a...a00 a...a01 a...a11 a...a10 a...a01 a...a00 burst address table (mode = gnd) first address (external) second address (internal) third address (internal) fourth address (internal) a...a00 a...a01 a...a10 a...a11 a...a01 a...a10 a...a11 a...a00 a...a10 a...a11 a...a00 a...a01 a...a11 a...a00 a...a01 a...a10 truth table [2, 3, 4, 5, 6, 7] operation address used ce ce2 ce2 adsp adsc adv write oe clk dq deselected cycle, power-down none h x x x l x x x l-h high-z deselected cycle, power-down none l x l l x x x x l-h high-z deselected cycle, power-down none l h x l x x x x l-h high-z deselected cycle, power-down none l x l h l x x x l-h high-z deselected cycle, power-down none l h x h l x x x l-h high-z read cycle, begin burst external l l h l x x x l l-h q read cycle, begin burst external l l h l x x x h l-h high-z write cycle, begin burst external l l h h l x l x l-h d read cycle, begin burst external l l h h l x h l l-h q read cycle, begin burst external l l h h l x h h l-h high-z read cycle, continue burst next x x x h h l h l l-h q read cycle, continue burst next x x x h h l h h l-h high-z read cycle, continue burst next h x x x h l h l l-h q read cycle, continue burst next h x x x h l h h l-h high-z write cycle, continue burst next x x x h h l l x l-h d write cycle, continue burst next h x x x h l l x l-h d read cycle, suspend burst current x x x h h h h l l-h q read cycle, suspend burst current x x x h h h h h l-h high-z notes: 2. x means ?don?t care.? h means logic high. l means logic low. write = l means [bwe + bwa *bwb *bwc *bwd ]*gw equals low. write = h means [bwe + bwa *bwb *bwc *bwd ]*gw equals high. bwa enables write to dqa. bwb enables write to dqb. bwc enables write to dqc. bwd enables write to dqd. 3. all inputs except oe must meet set-up and hold times around the rising edge (low to high) of clk. 4. suspending burst generates wait cycle. 5. for a write operation following a read operation, oe must be high before the input data required set-up time plus high-z time for oe and staying high throughout the input data hold time. 6. this device contains circuitr y that will ensure the outputs will be in high-z during power-up. 7. adsp low along with chip being selected always initiates a read cycle at the l-h edge of clk. a write cycle can be performed by set ting write low for the clk l-h edge of the subsequent wait cycle. refer to write timing diagram for clarification. [+] feedback
cy7c1347d document #: 38-05022 rev. *e page 6 of 21 ieee 1149.1 serial boundary scan (jtag) overview this device incorporates a serial boundary scan access port (tap). this port is designed to operate in a manner consistent with ieee standard 1149.1-1990 (commonly referred to as jtag), but does not implement al l of the functions required for ieee 1149.1 compliance. certain functions have been modified or eliminated because their implementation places extra delays in the critical speed path of the device. never- theless, the device supports the standard tap controller archi- tecture (the tap controller is th e state machine that controls the taps operation) and can be expected to function in a manner that does not conflict with the operation of devices with ieee standard 1149.1-compliant taps. the tap operates using lvttl/lvcmos logic level signaling. disabling the jtag feature it is possible to use this device without using the jtag feature. to disable the tap controller without interfering with normal operation of the device, tck should be tied low (v ss ) to prevent clocking the device. tdi and tms are internally pulled up and may be unconnected. they may alternately be pulled up to v cc through a resistor. tdo should be left unconnected. upon power-up the device will come up in a reset state which will not interfere with the operation of the device. test access port (tap) tck ?test clock (input) clocks all tap events. all input s are captured on the rising edge of tck and all outputs propagate from the falling edge of tck. tms ? test mode select (input) the tms input is sampled on the rising edge of tck. this is the command input for the tap controller state machine. it is allowable to leave this pin unconnected if the tap is not used. the pin is pulled up internally, resulting in a logic high level. tdi ?test data in (input) the tdi input is sampled on the rising edge of tck. this is the input side of the serial registers placed between tdi and tdo. the register placed between tdi and tdo is determined by the state of the tap controller state machine and the instruction that is currently loaded in the tap instruction register (refer to figure 1 ). it is allowable to leave this pin unconnected if it is not used in an application. the pin is pulled up internally, resulting in a logic high level. tdi is connected to the most significant bit (msb) of any register (see figure 2 ). tdo ? test data out (output) the tdo output pin is used to serially clock data-out from the registers. the output that is active depending on the state of the tap state machine (refer to figure 1 ). output changes in response to the falling edge of tck. this is the output side of the serial registers placed between tdi and tdo. tdo is connected to the least significant bit (lsb) of any register (see figure 2 ). performing a tap reset the tap circuitry does not have a reset pin (trst , which is optional in the ieee 1149.1 specification). a reset can be performed for the tap controll er by forcing tms high (v cc ) for five rising edges of tck and pre-loads the instruction register with the idcode co mmand. this type of reset does not affect the operation of the system logic. the reset affects test logic only. at power-up, the tap is reset in ternally to ensure that tdo is in a high-z state. test access port (tap) registers overview the various tap registers are selected (one at a time) via the sequences of ones and zeros input to the tms pin as the tck is strobed. each of the taps regi sters are serial shift registers that capture serial input data on the rising edge of tck and push serial data out on subsequent falling edge of tck. when a register is selected, it is connected between the tdi and tdo pins. read cycle, suspend burst current h x x x h h h l l-h q read cycle, suspend burst current h x x x h h h h l-h high-z write cycle, suspend burst current x x x h h h l x l-h d write cycle, suspend burst current h x x x h h l x l-h d truth table (continued) [2, 3, 4, 5, 6, 7] operation address used ce ce2 ce2 adsp adsc adv write oe clk dq partial truth table for read/write function gw bwe bwa bwb bwc bwd read h h x x x x read h l h h h h write one byte h l l h h h write all bytes h l l l l l write all bytes l x x x x x [+] feedback
cy7c1347d document #: 38-05022 rev. *e page 7 of 21 instruction register the instruction register holds the instructions that are executed by the tap controller when it is moved into the run test/idle or the various data re gister states. the instructions are three bits long. the register can be loaded when it is placed between the tdi and tdo pins. the parallel outputs of the instruction register are automatically preloaded with the idcode instruction upon power-u p or whenever the controller is placed in the test-logic reset state. when the tap controller is in the capture-ir state, the two least significant bits of the serial instruction register are lo aded with a binary ?01? pattern to allow for fault isolation of the board-level serial test data path. bypass register the bypass register is a single-b it register that can be placed between tdi and tdo. it allows serial test data to be passed through the device tap to another device in the scan chain with minimum delay. the bypass register is set low (v ss ) when the bypass instruction is executed. boundary scan register the boundary scan register is connected to all the input and bidirectional i/o pins (not coun ting the tap pins) on the device. this also includes a number of nc pins that are reserved for future needs. there are a total of 70 bits for x36 device and 51 bits for x18 device. the boundary scan register, under the control of the tap controller, is loaded with the contents of the device i/o ring when the controller is in capture-dr state and then is placed between the tdi and tdo pins when the controller is moved to shif t-dr state. the extest, sample/ preload and sample-z instructions can be used to capture the contents of the i/o ring. the boundary scan order table describes the order in which the bits are connected. the first column defines the bit?s position in the boundary scan register. the msb of the register is connected to tdi, and lsb is connected to tdo. the second column is the signal name and the third column is the bump number. the third column is the tqfp pin number and the fourth column is the bga bump number. identifica tion (id) register the id register is a 32-bit regi ster that is loaded with a device and vendor specific 32-bit code when the controller is put in capture-dr state wit h the idcode command loaded in the instruction register. the register is then placed between the tdi and tdo pins when the controller is moved into shift-dr state. bit 0 in the register is the lsb and the first to reach tdo when shifting begins. the code is loaded from a 32-bit on-chip rom. it describes various attributes of the device as described in the identification register definitions table. tap controller instruction set overview there are two classes of instructions defined in the ieee standard 1149.1-1990; the standard (public) instructions and device specific (private) instru ctions. some public instructions are mandatory for ieee 1149.1 compliance. optional public instructions must be impl emented in prescribed ways. although the tap controller in this device follows the ieee 1149.1 conventions, it is not ieee 1149.1 compliant because some of the mandatory instructions are not fully implemented. the tap on this device may be used to monitor all input and i/o pads, but can not be used to load address, data, or control signals into the device or to preload the i/o buffers. in other words, the device will not perform ieee 1149.1 extest, intest, or the preload portion of the sample/preload command. when the tap controller is placed in capture-ir state, the two least significant bits of the in struction register are loaded with 01. when the controller is move d to the shift-ir state the instruction is serially loaded through the tdi input (while the previous contents are shifted out at tdo). for all instructions, the tap executes newly loaded instructions only when the controller is moved to update-ir state. the tap instruction sets for this device are listed in the following tables. extest extest is an ieee 1149.1 mandatory public instruction. it is to be executed whenever the in struction register is loaded with all 0s. extest is not implemented in this device. the tap controller does recogn ize an all-0 instruction. when an extest instruction is loaded into the instruction register, the device responds as if a sample/preload instruction has been loaded. there is one difference between two instruc- tions. unlike sample/preloa d instruction, extest places the device outputs in a high-z state. idcode the idcode instruction causes a vendor-specific, 32-bit code to be loaded into the id register when the controller is in capture-dr mode and places the id register between the tdi and tdo pins in shift-dr mode. the idcode instruction is the default instruction loaded in the instruction upon power-up and at any time the tap controller is placed in the test-logic reset state. sample-z if the high-z instruction is loaded in the instruction register, all output pins are forced to a high-z state and the boundary scan register is connected between tdi and tdo pins when the tap controller is in a shift-dr state. sample/preload sample/preload is an ieee 1149.1 mandatory instruction. the preload portion of the command is not implemented in this device, so the device tap controller is not fully ieee 1149.1-compliant. when the sample/preload instruction is loaded in the instruction register and the tap controller is in the capture-dr state, a snap shot of the data in the device?s input and i/o buffers is loaded into the boundary scan register. because the device system clock(s) are independent from the tap clock (tck), it is possible for the tap to attempt to capture the input and i/o ring contents while the buffers are in transition (i.e., in a metastable state). although allowing the tap to sample metastable inputs will not harm the device, repeatable results can not be expected. to guarantee that the boundary scan register will capture the correct value of a signal, the device input signals must be stabilized long enough to meet the tap controller?s capture setup plus hold time (t cs plus t ch ). the device clock input(s) need not be paused for any other tap operation except capturing the i nput and i/o ring contents into the boundary scan register. [+] feedback
cy7c1347d document #: 38-05022 rev. *e page 8 of 21 moving the controller to shift-dr state then places the boundary scan register between the tdi and tdo pins. because the preload portion of the command is not imple- mented in this device, moving the controller to the update-dr state with the sample/preload instruction loaded in the instruction register has the same effect as the pause-dr command. bypass when the bypass instruction is loaded in t he instruction register and the tap controller is in the shift-dr state, the bypass register is placed between tdi and tdo. this allows the board level scan path to be shortened to facilitate testing of other devices in the scan path. reserved do not use these instructions. they are reserved for future use. note: 8. the 0/1 next to each state represents the value at tms at the rising edge of tck. test-logic reset reun-test/ idle select dr-scan capture-dr shift-dr exit1-dr pause-dr exit2-dr update-dr select ir-scan capture-ir shift-ir exit1-ir pause-ir exit2-ir update-ir 1 0 1 1 0 1 0 1 0 0 0 1 1 1 0 1 0 1 0 0 0 1 0 1 1 0 1 0 0 1 1 0 figure 1. tap controller state diagram [8] [+] feedback
cy7c1347d document #: 38-05022 rev. *e page 9 of 21 0 0 1 2 . . 29 30 31 boundary scan register identification register 0 1 2 . . . . x 0 1 2 instruction register bypass register selection circuitry selection circuitry tap controller tdi tdo tdi tdi [9] figure 2. tap contro ller block diagram tap dc electrical characteristics (20c < t j < 110c; v cc = 3.3v ?0.2v and +0.3v unless otherwise noted) parameter description test conditions min. max. unit v ih input high (logic 1) voltage: inputs [10, 11] v ccq = 3.3 v 2.0 4.6 v v ccq = 2.5v 1.7 4.6 v input high (logic 1) voltage: data [10, 11] v ccq = 3.3 v 2.0 v ccq + 0.3 v v ccq = 2.5v 1.7 v ccq + 0.3 v il input low (logic 0) voltage: inputs and data [10, 11] v ccq = 3.3 v ?0.5 0.8 v v ccq = 2.5v ?0.3 0.7 v il i input leakage current 0v < v in < v cc ?5.0 5.0 a il i tms and tdi input leakage current 0v < v in < v cc ?30 30 a il o output leakage current output disabled, 0v < v in < v ccq ?5.0 5.0 a v olc lvcmos output low voltage [10, 12] i olc = 100 a0.2v v ohc lvcmos output high voltage [10, 12] i ohc = 100 av ccq ? 0.2 v notes: 9. x = 69. 10. all voltage referenced to v ss (gnd). 11. overshoot: v ih (ac)< v cc + 1.5v for t< t khkh /2, undershoot: v il (ac)< ?0.5v for t< t khkh /2, power-up: v ih < 3.6v and v cc < 3.135v and v ccq < 1.4v for t< 200 ms. during normal operation, v ccq must not exceed 3.6v. control input signals (such as r/w , adv/ld , etc.) may not have pulse widths less than t khkl (min.). 12. this parameter is sampled. [+] feedback
cy7c1347d document #: 38-05022 rev. *e page 10 of 21 v olt lvttl output low voltage [10] v cc = min. v ccq = 3.3 v, i olt = 8.0 ma 0.4 v v cc = min. v ccq = 2.5v, i olt = 2.0 ma 0.7 v v cc = min. v ccq = 2.5v, i olt = 1.0 ma 0.4 v v oht lvttl output high voltage [10] v cc = min. v ccq = 3.3 v, i oh = ?4.0 ma 2.4 v v cc = min, v ccq = 2.5v, i oh = ?2.0 ma 2.0 v tap ac switching characteristics over the operating range [13, 14] parameter description min. max unit clock t thth clock cycle time 20 ns f tf clock frequency 50 mhz t thtl clock high time 8 ns t tlth clock low time 8 ns output times t tlqx tck low to tdo unknown 0 ns t tlqv tck low to tdo valid 10 ns t dvth tdi valid to tck high 5 ns t thdx tck high to tdi invalid 5 ns set-up times t mvth tms set-up 5 ns t cs capture set-up 5 ns hold times t thmx tms hold 5 ns t ch capture hold 5 ns notes: 13. t cs and t ch refer to the set-up and hold time requirements of latching data from the boundary scan register. 14. test conditions are specified using the load in tap ac test conditions. tap dc electrical characteristics (20c < t j < 110c; v cc = 3.3v ?0.2v and +0.3v unl ess otherwise noted) (continued) parameter description test conditions min. max. unit [+] feedback
cy7c1347d document #: 38-05022 rev. *e page 11 of 21 tap timing and test conditions identification register definitions instruction field 128k x 36 description revision number (31:28) xxxx reserved for revision number. device depth (27:23) 00111 defines depth of words. device width (22:18) 00011 defines width of bits. reserved (17:12) xxxxxx reserved for future use. cypress jedec id code (11:1) 00011100100 allows unique identification of device vendor. id register presence indicator (0) 1 indicates the presence of an id register. (a) 3.3v / 2.5v v ss all input pulses 1.5v 1.5 ns 1.5 ns vt = 1.5v tdo z 0 = 50 ? 50 ? 20 pf for 3.3v vccq or v ccq /2 for 2.5v v ccq test clock (tck) t thth t thtl t tlth test mode select (tms) test data in (tdi) test data out (tdo) t mvth t thmx t dvth t thdx t tlqx t tlqv scan register sizes register name bit size (x36) instruction 3 bypass 1 id 32 boundary scan 51 [+] feedback
cy7c1347d document #: 38-05022 rev. *e page 12 of 21 instruction codes instruction code description extest 000 captures i/o ring contents. places the bou ndary scan register between tdi and tdo. forces all device outputs to high-z state. this in struction is not i eee 1149.1-compliant. idcode 001 preloads id register with vendor id code and places it between tdi and tdo. this instruction does not affect device operations. sample-z 010 captures i/o ring contents. places the boundary scan register between tdi and tdo. forces all device outputs to high-z state. reserved 011 do not use these instructions ; they are reserved for future use. sample/preload 100 captures i/o ring contents. places the boundary scan register between tdi and tdo. this instruction does not affect devic e operations. this in struction does not implement ieee 1149.1 preload function and is ther efore not 1149.1-compliant. reserved 101 do not use these instructions; they are reserved for future use. reserved 110 do not use these instructions ; they are reserved for future use. bypass 111 places the bypass register between tdi and td o. this instruction does not affect device opera- tions. boundary scan order bit# signal name tqfp bump id 1a442r 2a453t 3a464t 4a475t 5a486r 6a493b 7a505b 8dqa516p 9dqa527n 10dqa536m 11 dqa 56 7l 12 dqa 57 6k 13 dqa 58 7p 14 dqa 59 6n 15 dqa 62 6l 16 dqa 63 7k 17 zz 64 7t 18 dqb 68 6h 19 dqb 69 7g 20 dqb 72 6f 21 dqb 73 7e 22 dqb 74 6d 23 dqb 75 7h 24 dqb 78 6g 25 dqb 79 6e 26 dqb 80 7d 27 a 81 6a 28 a 82 5a 29 adv 83 4g 30 adsp 84 4a 31 adsc 85 4b 32 oe 86 64f 33 bwe 87 4m 34 gw 88 4h 35 clk 89 4k 36 ce 2 92 6b 37 bwa 93 5l 38 bwb 94 5g 39 bwc 95 3g 40 bwd 96 3l 41 ce 2 97 2b 42 ce 98 4e 43 a 99 3a 44 a 100 2a 45 dqc 1 2d 46 dqc 2 1e 47 dqc 3 2f 48 dqc 6 1g 49 dqc 7 2h 50 dqc 8 1d 51 dqc 9 2e 52 dqc 12 2g 53 dqc 13 1h 54 nc 14 5r 55 dqd 18 2k 56 dqd 19 1l 57 dqd 22 2m 58 dqd 23 1n boundary scan order (continued) bit# signal name tqfp bump id [+] feedback
cy7c1347d document #: 38-05022 rev. *e page 13 of 21 59 dqd 24 2p 60 dqd 25 1k 61 dqd 28 2l 62 dqd 29 2n 63 dqd 30 1p 64 mode 31 3r 65 a 32 2c 66 a 33 3c 67 a 34 5c 68 a 35 6c 69 a1 36 4n 70 a0 37 4p boundary scan order (continued) bit# signal name tqfp bump id [+] feedback
cy7c1347d document #: 38-05022 rev. *e page 14 of 21 maximum ratings (above which the useful life may be impaired. for user guide- lines, not tested.) voltage on v cc supply relative to v ss ......... ?0.5v to +4.6v v in ...........................................................?0.5v to v cc +0.5v storage temperature (plastic) ...................... ?55c to +150 junction temperature ..................................................+150 power dissipation.......................................................... 1.0w short circuit output current ........................................ 50 ma operating range range ambient temperature [15] v cc com?l 0c to +70c 3.3v ? 5%/+10% electrical characteristics over the operating range parameter description test conditions min. max. unit v ih input high (logic 1) voltage: inputs [10, 11] v ccq = 3.3 v 2.0 4.6 v v ccq = 2.5v 1.7 4.6 v input high (logic 1) voltage: data [10, 11] v ccq = 3.3 v 2.0 v ccq + 0.3 v v ccq = 2.5v 1.7 v ccq + 0.3 v il input low (logic 0) voltage: inputs and data [10, 11] v ccq = 3.3 v ?0.5 0.8 v v ccq = 2.5v ?0.3 0.7 v il i input leakage current 0v < v in < v cc ?5 5 a il i mode and zz input leakage current [17] 0v < v in < v cc ?30 30 a il o output leakage current output(s) disabled, 0v < v out < v cc ?5 5 a v oh output high voltage [10] v cc = min, v ccq = 3.3 v, i oh = ?4.0 ma 2.4 v v cc = min, v ccq = 2.5v, i oh = ?2.0 ma 2.0 v v ol output low voltage [10] v cc = min, v ccq = 3.3v, i ol = 8.0 ma 0.4 v v cc = min, v ccq = 2.5v, i oh = 2.0 ma 0.7 v v cc = min, v ccq = 2.5v, i oh = 1.0 ma 0.4 v vcc supply voltage [10] 3.135 3.6 v vccq i/o supply voltage [10] 3.3 v range 3.135 3.6 v 2.5 v range 2.375 2.9 v parameter description conditions typ. -4 -4.4 -5 -6 unit i cc power supply current: operating [18, 19, 20] device selected; all inputs < v il or > v ih ; cycle time > t kc min.; v cc = max.; outputs open 150 450 400 360 300 ma i sb2 cmos standby [19, 20] device deselected; v cc = max.; all inputs < v ss + 0.2 or > v cc ? 0.2; all inputs static; clk frequency = 0 5 10101010ma i sb3 ttl standby [19, 20] device deselected; all inputs < v il or > v ih ; all inputs static; v cc = max.; clk frequency = 0 10 20 20 20 20 ma i sb4 clock running [19, 20] device deselected; all inputs < v il or > v ih ; v cc = max.; clk cycle time > t kc min. 40 140 125 110 90 ma notes: 15. t a is the case temperature. 16. overshoot: v ih +6.0v for t t kc /2. undershoot:v il ?2.0v for t t kc /2. 17. output loading is specified with c l = 5 pf as in ac test loads. 18. i cc is given with no output current. i cc increases with greater output loading and faster cycle times. 19. ?device deselected? means the device is in power-down mode as defined in the truth table. ?device selected? means the device is active. 20. typical values are measured at 3.3v, 25c, and 20-ns cycle time. [+] feedback
cy7c1347d document #: 38-05022 rev. *e page 15 of 21 capacitance [12] parameter description test conditions typ. max. unit c i input capacitance t a = 25 c, f = 1 mhz, v cc = 3.3v 57 pf c o input/output capacitance (dq) 7 8 pf thermal resistance parameter description test conditions tqfp typ. bga typ. unit ja thermal resistance (junction to ambient) still air, soldered on a 4.25 x 1.125 inch, 4-layer pcb 25 50 c/w jc thermal resistance (j unction to case) 9 8 c/w ac test loads and waveforms [21] switching characteristics over the operating range [22] parameter description 250 mhz 225 mhz 200 mhz 166 mhz unit min. max. min. max. min. max. min. max. clock tkc clock cycle time 4.0 4.4 5.0 6.0 ns tkh clock high time 1.6 1.7 2.0 2.4 ns tkl clock low time 1.6 1.7 2.0 2.4 ns output times tkq clock to output valid 2.4 2.5 3.0 3.5 ns tkqx clock to output invalid 1.25 1.25 1.25 1.25 ns tkqlz clock to output in low-z [12, 17, 23] 0000ns tkqhz clock to output in high-z [12, 17, 23] 1.25 3.0 1.25 3.0 1.25 3.0 1.25 4.0 ns toeq oe to output valid [24] 2.5 2.5 2.5 3.5 ns toelz oe to output in low-z [12, 17, 23] 0000ns toehz oe to output in high-z [12, 17, 23] 2.5 2.5 2.5 3.5 ns set-up times ts address, controls, and data in [25] 1.5 1.5 1.5 1.5 ns hold times th address, controls, and data in [25] 0.5 0.5 0.5 0.5 ns notes: 21. overshoot: vih(ac) < vdd + 1.5v for t < ttcyc/2; undershoot: vil(ac) < 0.5v for t < ttcyc/2; power-up: vih < 2.6v and vdd < 2.4v and vddq < 1.4v for t < 200 ms. 22. test conditions as specified with the output loading as shown in part (a) of ac test loads unless otherwise noted. 23. at any given temperature and voltage condition, t kqhz is less than t kqlz and t oehz is less than t oelz . 24. oe is a ?don?t care? when a byte write enable is sampled low. 25. this is a synchronous dev ice. all synchronous inputs must meet specified set-up and hold time, except for ?don?t care? as defined in the truth table. 317 ? / 225 ? 351 ? 5pf (a) (b) dq 50 ? z 0 =50 ? v t = 1.5vfor 3.3v v ccq 3.3v / 2.5v all input pulses 3.3v / 2.5v 0v 90% 10% 90% 10% 1.5 ns 1.5 ns (c) or v ccq /2 for 2.5v v ccq dq / 225 ? [+] feedback
cy7c1347d document #: 38-05022 rev. *e page 16 of 21 typical output buffer characteristics output high voltage pull-up current output low voltage pull-down current v oh (v) i oh (ma) min. i oh (ma) max. v ol (v) i ol (ma) min. i ol (ma) max. ?0.5 ?38 ?105 ?0.5 0 0 0 ?38 ?105 0 0 0 0.8 ?38 ?105 0.4 10 20 1.25 ?26 ?83 0.8 20 40 1.5 ?20 ?70 1.25 31 63 2.3 0 ?30 1.6 40 80 2.7 0 ?10 2.8 40 80 2.9 0 0 3.2 40 80 3.4 0 0 3.4 40 80 switching waveforms read timing [26, 27] notes: 26. ce active in this timing diagram means that all chip enables ce , ce2, and ce2 are active. 27. for x18 product, there are only bwa and bwb for byte write control. clk adsp# adsc# address bwa#, bwb#, bwc#, bwd#, bwe#, gw# ce# adv# oe# dq a1 a2 q(a1) q(a2) q(a2+1) q(a2+2) q(a2+3) q(a2) q(a2+1) t kq t kqlz t oelz t kq t s t h t kh t kl t kc t oeq single read burst read t h t h t s t s t s [+] feedback
cy7c1347d document #: 38-05022 rev. *e page 17 of 21 write timing [26, 27] switching waveforms (continued) clk adsp# adsc# address ce# adv# oe# dq a1 a2 d(a2) d(a2+2) d(a2+3) d(a3) d(a3+1) d(a3+2) t s t h gw# a3 d(a1) d(a2+1) t kqx t oehz q d(a2+1) single write burst write burst write t h t h t s t s bwa#, bwb#, bwc#, bwd#, bwe#, gw# [+] feedback
cy7c1347d document #: 38-05022 rev. *e page 18 of 21 read/write timing [26, 27] ordering information speed (mhz) ordering code package name package type operating range 250 cy7c1347d-250ac a101 100-lead 14 x 20 x 1.4 mm thin quad flat pack commercial cy7c1347d-250bgc bg119 119-lead fbga (14 x 22 x 2.4 mm) 225 cy7c1347d-225bgc bg119 119-lead fbga (14 x 22 x 2.4 mm) 200 cy7c1347d-200ac a101 100-lead 14 x 20 x 1.4 mm thin quad flat pack 166 CY7C1347D-166AC a101 100-lead 14 x 20 x 1.4 mm thin quad flat pack switching waveforms (continued) clk adsp# adsc# address ce# adv# oe# dq a1 a2 a3 q(a1) q(a2) t s t h t s t h a4 d(a3) q(a4) q(a4+1) q(a4+2) d(a5) d(a5+1) single write burst read burst write single reads a5 bwa#, bwb#, bwc#, bwd#, bwe#, gw# [+] feedback
cy7c1347d document #: 38-05022 rev. *e page 19 of 21 package diagrams 100-pin thin plastic quad flatpack (14 x 20 x 1.4 mm) a101 51-85050-*a [+] feedback
cy7c1347d document #: 38-05022 rev. *e page 20 of 21 ? cypress semiconductor corporation, 2004. the information contained herein is subject to change without notice. cypress semic onductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or ot her rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agr eement with cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to re sult in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manu facturer assumes all risk of such use and in doing so indemni fies cypress against all charges. all product and company names mentio ned in this document may be the tr ademarks of their respective holders. package diagrams (continued) 51-85115-*b 119-lead fbga (14 x 22 x 2.4 mm) bg119 [+] feedback
cy7c1347d document #: 38-05022 rev. *e page 21 of 21 document history page document title: cy7c1347d: 128k x 36 synchronous-pipelined cache sram document number: 38-05022 rev. ecn no. issue date orig. of change description of change ** 106740 05/07/01 rcs new data sheet *a 107485 06/06/01 rcs added minimum and maximum values for 2.5v v ccq and all other subsequent parameters defined alternate options for non-utilized jtag pins *b 121064 11/13/02 dsg updated package drawing 51-85115 (bg119) to rev. *b *c 122474 01/18/03 rbi added power up requirements to ac test loads and waveforms information *d 212291 see ecn vbl corrected ordering info section : delete 166bga, 200bga, 225ac *e 289731 see ecn njy corrected the typo on page 4 for tms pin connection [+] feedback

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